ADZS-TS201S-EZLITE,適用于 TigerSHARC 浮點
嵌入式處理器的 ADSP-TS201S EZ-KIT Lite 評估系統(tǒng)。 TigerSHARC 處理器是一種靜態(tài)超標(biāo)量 (SSS) 架構(gòu),針對軟件定義
無線電應(yīng)用。在這些無線基礎(chǔ)設(shè)施應(yīng)用中,TigerSHARC 處理器正在取代第三代蜂窩芯片速率處理應(yīng)用中的
現(xiàn)場可編程門陣列 (FPGA)。 TigerSHARC 處理器的性能、靈活性、多處理和 IO 功能使其優(yōu)于 FPGA 實現(xiàn)。該評估板設(shè)計用于與VisualDSP++開發(fā)環(huán)境配合使用,以測試ADSP-TS201S TigerSHARC處理器的功能。 VisualDSP++開發(fā)環(huán)境使您能夠執(zhí)行高級應(yīng)用
程序代碼開發(fā)
說明
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ADZS-TS201S-EZLITE, ADSP-TS201S EZ-KIT Lite Evaluation System for TigerSHARC floating-point embedded processors. The TigerSHARC processor is a static super scalar (SSS) architecture targeted at software-defined radio applications. In these wireless infrastructure applications, the TigerSHARC processor is replacing field-programmable gate arrays (FPGAs) in the chip rate processing applications for third generation cellular. The performance, flexibility, multiprocessing and IO capabilities of the TigerSHARC processor makes it superior to FPGA implementations. The evaluation board is designed to be used in conjunction with the VisualDSP++ development environment to test the capabilities of the ADSP-TS201S TigerSHARC processor. The VisualDSP++ development environment gives you the ability to perform advanced application code development
主要特色
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Embedded System Type
DSP
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Family Name
TigerSHARC
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Platform
EZ-KIT Lite